This looks like different TI product, what makes you believe it is significantly similar to IVA?

As for the mailbox and driver stuff - even if we know which mailbox is used to communicate with IVA there is lot of additional stuff needed just like for C55 DSP. We first need to boot the IVA arm core with some code so it could actually communicate with main ARM core. So in addition to extending dspgateway for IVA we would need also some sort of IVA BIOS and access to OMAP registers that can poweron/reset/configure IVA (just like there is such stuff for the DSP).

Yes, IVA 2 have CPU ARM968 and DSP C64x+...but I said FUNCTIONALLY... because I think that registers (with some differences), mode to setup registers and to compute data are similar...

and above all ... I hope to unlocking there periferials...

Hi fanoush,

read this paper (TI paper) page 20

http://www.ti.com/asia/docs/india/ti.../ramkishor.pdf

I see, "Accelerators of DM270 are used (IVA)". So indeed it looks like IVA in OMAP2420 uses some accelerators from DM270. That's good to know, thanks. Still it doesn't mean IVA = DM270. Most of DM270 info is not directly applicable except programming info for those accelerator modules. Once someone manages to run something on that ARM7TDMI this will be helpful.

IVA2 has no ARM CPU. If I understand it correctly IVA 2 on OMAP3 chips is just marketiing name for the DSP.

fanoush,

I thought the IVA was just a DSP with a few extra bits sprinkled ontop for extra image manipulation.
They basically do the same job and its simple enough to duplicate the silicon pattern.
It doesnt make sense for the IVA to share the same physical core as the audio focused DSP because they both need to work simultainiously.

I spoke this morning with a TI enginneer... There is an ARM9 into IVA2 ;-)

See these :
OMAP2420
VPOM-2420 models all the components listed as well as the entire user interface from device interface to touch-screen, stylus and terminals. The platform integrates with the most important software development tools available for the OMAP technology.

DSP Subsystem:

UMA 2.3, MMU, IRQ ctrl L2, DSP DMA, IPI
MPU Subsystem:

ARM1136F-S, IRQ Ctrl
Interconnect:

L3, L4
Peripherals:

System DMA, UARTx3, GPTx12, WDTx3, 32k Synchro Counter, Mailbox, GPIOx4, I2Cx2, McBSPx2, McSPIx2, FAC, SSI, HDQ/1 wire, Window Tracer, EAC, MMC/SDIO
Host Peripherals:

USB OTG, SSI, VLYNQ
Security:

RNG, DES/3DES, SHA1/MD5, AES, PKA, Secure WDT, e-fuse
Memory Controllers:

SMS, SDRC, GPMC
System Controls:

PRCM (Core, DSP, GFX, WAKEUP)
Multimedia:

Display Subsystem (LCD Controller), Camera Subsystem, 2D/3D Graphics
IVA 1.0 :

ARM7TDMIE, iINTC, System Controller, REGS2, MMU, sINTC, IVA Registers, RAM, VLCD, IMX, SEQ, DMA
SDP:

LAN91C96 Ethernet, SDRAM, System Power Manager (TWL92230), NOR Flash (Intel StrataFlash 28F256L18), NAND Flash (Samsung K9F5608(16)), TSC2101 Audio Codec and TouchScreen controller, Epson RTC8564, Omnivision OV9640 camera, Device/Revision Info Serial EEPROM (M24C01RMN), I2C I/O Expanders (PCF8574PWR), MMC/SD, USBOTG Transceiver (ISP1301BS), FPGA, LCD and Keypad


OMAP3430

MPU Subsystem:
ARM Ferrari including VFPv3, NEON; IRQ Ctrl, L2 cache ARM's Cortex-A Model integration
Interconnect:
L3 (SMX-APE), Wakeup L4, Per L4
System DMA Peripherals:
UARTx3, GPTx12 (1,2,10: 1MS), WDTx3, 32k Synchro Counter, Mailbox, GPIOx6, MSHSI2Cx3, McBSPx5, SPIx4, FAC, SSI, HDQ/1 wire, HS MMC/SDIOx2, MS-PRO/MG (stub), ICR, Modem Interrupt Handler (stub)
Host Peripherals:
USB OTG, USB HS OTG, SSI

Security:
RNG, DES/3DESx2, SHA1/MD5x2, AESx2, Fast PKA (Safenet EIP-29), e-fuse
Memory Controllers:
SMS, SDRC, GPMC

On-Chip Memory:
96 Kbytes ROM, 64 Kbytes SRAM
System Controls:


PRCM, Voltage Controller (PRM), SmartReflex 5000X x 2, Voltage Processor x 2
Multimedia:
Display Subsystem (LCD Controller), Camera Subsystem ISP, 2D/3D Graphics
IVA2+:
C64x+ (Joule), L1 Program Memory Controller (PMC), L1 Data Memory Controller (DMC), Unified Memory Controller (UMC), Extended Memory Controller (EMC) including IDMA, SYS module, Power-Down & Reset Controller (PDC), Interrupt Controller (IC) L1 Program Cache, L1 Program RAM, L1 Data Cache L1 Data RAM, L2 Unified Cache, L2 ROM, L2 RAM EDMA 3.0, MMU, HPI, System Controller (SYSC) Wake-Up Generator (WUGEN), IVA2 configuration registers
LEON:
ARM968E-S, ITCM, DTCM, LeSS configuration registers, LEON configuration registers, SCRO, LCKG, iVLCD, iME, iLF
H4 Development Board (SDP):
LAN91C96 Ethernet, SDRAM NOR Flash (Intel StrataFlash 28F256L18), NAND Flash (Samsung K9F5608(16)), TSC21001 Audio Codec and TouchScreen controller, Epson RTC8564, Omnivision OV9640 camera, FPGA, LCD, Keypad, Device/Revision Info Serial EEPROM (M24C01RMN), I2C I/O Expanders (PCF8574PWR), MMC, SD, TWL4030 Audio/Power Mangement ICs

read page 1993 of SWPU114I_PrelimFinalEPDF_06_10_2008.pdf


The sequencer module, referred to as sequencer or video sequencer, is an ARM968E-S based
microcontroller that handles maintenance functions for the video hardware accelerators implemented in
IVA2.2.

IVA in the OMAP3xxx is a C6x DSP + bits, IVA in the OMAP2xxx is an ARM9 core + coprocessors. There is no C6x DSP in the OMAP2xxx.

It looks like the same coprocessors are used in both though - see overflo's post 2 up from this one & the DM270 datasheet (VLC & iMX)

I found on internet some files about mapping of memory into OMAP2420, is it possible upload these file on this thread... I think they are useful...