
[91202.267547] WARNING: at /home/builder1/maemo-fremantle-armel-extras-devel/work/kernel-maemo-2.6.28/arch/arm/mach-omap2/clock34xx.c:443 omap3_noncore_dpll_set_rate+0x28c/0x2dc() ...
[91202.267547] WARNING: at /home/builder1/maemo-fremantle-armel-extras-devel/work/kernel-maemo-2.6.28/arch/arm/mach-omap2/clock34xx.c:443 omap3_noncore_dpll_set_rate+0x28c/0x2dc()


freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
if (!freqsel)
WARN_ON(1);
* CORE DPLL (DPLL3) rate programming functions * * These call into SRAM code to do the actual CM writes, since the SDRAM * is clocked from DPLL3.
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